1. Field of the Invention
This invention relates generally to semiconductor storage devices for use in random access memory arrays. More specifically, it relates to a nondestructive read-out device and memory cell which are capable of being placed in two states; one stable and the other quasi-stable. Still more specifically, it relates to a device and memory cell which, by the application of appropriate biases and appropriately poled pulse potentials, can be caused to enter a deep depletion or nonconductive state or an inversion or conductive state. Still more specifically, it relates to a memory cell which includes an addressing FET disposed on the same substrate which is connected in series with the storage device. The former device is connected by its gate to a word line while the source thereof it connected to a source of pulsed potentials which set the storage device in one or the other of its two possible states. The arrangement results in a single memory storage device capable of nondestructive read-out. It is characterized by relatively long retention time and a minimum of stand-by power. The structure of the device and the memory cell may be fabricated using well-known semiconductor fabrication techniques.
2. Description of the Prior Art
U.S. Pat. No. 3,439,236 filed Dec. 9, 1965, issued Apr. 15, 1969 and entitled "Insulated Gate Field Effect Transistor with Critical Bulk Characteristics for Use as an Oscillator Component" shows in FIG. 1 thereof a structure which includes a pair of N+ diffusions in a P conductivity type substrate which are joined by an N conductivity type diffusion. The reference also includes an insulated gate disposed over the diffused channel region. The device of the reference may be operated in two different modes, which are analogous to the operation of an insulated gate field effect transistor in the enhancement mode and in the depletion mode. In the depletion mode of operation, a DC potential is applied between a source and drain providing an electric field which is above the threshold value for the particular semiconductor employed, so that current oscillations are being produced between the source and drain. A signal source connected to the gate electrode of the device now provides a negative bias to the gate electrode. The negatively charged gate electrode repels the negative charge carriers from the N conductivity type diffused region which corresponds to the channel of an insulated gate field effect transistor. The number of charge carriers (electron) in the channel region is thus depleted. When the concentration of majority carriers in the N conductivity type diffused region is reduced below a critical value, such that the product of the number of electrons/cm.sup.2 times the length of the N conductivity type region in cm is less than about 10.sup.11 /cm.sup.2, then the oscillations will cease. In the enhancement mode of operation, a DC source provides an electric field between source and drain which is below the critical value required for the particular semiconductor employed. Accordingly, no current oscillations will be observed. The signal source connected to the source and drain then provides a positive bias to the gate electrode. The positively charged gate electrode attracts additional negative charge carriers into the N conductivity type region. When the concentration of charge carriers (electrons) in the N conductivity type diffused region is increased above a critical value, such that the product of the number of electrons/cm.sup.3 times the length of N conductivity type diffused region in cm is greater than about 10.sup.11 /cm.sup.2, then current oscillations will occur in the device between the source and drain of the device. Thus, while the structure of the device of the reference is the same as that of the present storage device, there are no potentials applied which would cause the device to assume two states under the same bias conditions nor any indication that the surface of the channel region must be isolated from the device substrate.
An article entitled "Deep Channel MOS Transistor" by J. Berger in IEEE Transactions on Electron Devices, Vol. ED-22, No. 6, June 1975, p. 314 shows an ion-implanted MOS transistor which functions as an integrating, nondestructively readable photosensor which is fabricated using a technology which is fully compatible with advanced MOS integrated circuits. The device utilizes both P and N conductivity type buried channels in the region between source and drain. A gate electrode is disposed in insulated spaced relationship with respect to the P and N conductivity type implanted channels. With zero voltage on the gate electrode, the channel region of the same conductivity type as the source and drain and disposed below an opposite conductivity ionimplanted region is on or conductive and current can pass between source and drain. When a large negative potential is applied to the gate electrode, all the minority carriers existing in the depletion layer are attracted to the interface and the channel is turned off by depletion. The charge storage region (the implanted region of the same conductivity type as the substrate) is now capable of storing a large positive charge. Since this region is not connected with the substrate, the charge storage region remains depleted until thermal (or light) generation produces enough minority carriers. When the total positive charge in the charge storage region increases, it gradually screens off the channel region by terminating the electric field imposed by the gate electrode and hence, the channel will slowly become conductive.
The device of the article, while it turns the channel off by depletion as does the device of the present application, it appears to require the implantation of a region of the same conductivity type as the substrate at the surface of what would normally be the channel of an MOS transistor. The present device is distinguishable over the reference in that the device of the present application does not require the physical presence of a layer at the surface which is the same as the conductivity type of the device substrate. By utilizing a bias, an inversion layer is electrically generated during the stable state of the device permitting the applied electric field to be terminated on said layer and dropping most of the applied bias potential in the insulating layer. There is no hint or suggestion in either of the references cited as to how a device containing a single buried channel may be operated in a stable condition by utilizing an inversion layer.